I. Field of the Invention
This invention relates to a semiconductor device comprising a gate electrode of high melting metal provided in a self-alignment fashion, and, more particularly, to a super high frequency transistor and the method of manufacturing the same.
II. Description of the Prior Art
When a super high frequency semiconductor device is manufactured, mask alignment should be effected with a precision of .+-.1 micron in the formation of the various regions of a substrate and an electrode. However, the ordinary photoengraving process has the drawbacks that variations arise in the channel length and source resistance, which are parameters in defining the property of a semiconductor device, because mask alignment is carried out with low precision; the device itself presents variations in its property and has a low yield; and, moreover, the manufacture of said device involves complex processing.
For the resolution of the above-mentioned difficulties, the so-called self-alignment method has been proposed, this method comprising the steps of:
forming on a substrate a gate electrode prepared from such a high melting metal as can withstand the high temperature heat treatment required for the activation of an ion-implanted layer; and PA1 ion-implanting an impurity into the substrate using said gate electrode as a mask. PA1 a semiconductor compound substrate on the surface of which there are deposited a source region, a drain region and an intervening channel region; PA1 a source electrode formed on said source region; PA1 a drain electrode formed on said drain region; and PA1 a 3-ply gate electrode provided on said channel region, said gate electrode consisting of a high melting metal layer, a barrier metal layer and a gold layer in that order. PA1 forming a high melting metal layer, a barrier metal layer and a gold layer on an active layer formed on a compound semiconductor substrate in the order mentioned; PA1 patterning said gold layer, barrier metal layer and high melting layer in the same pattern, thus forming a 3-ply gate electrode; PA1 mounting an insulating film over the entire surface of said substrate including the surface of said gate electrode; PA1 ion-implanting, in said substrate, an impurity of the same conductivity type as said active layer using as a mask said gate electrode and the insulating film formed on the side wall of said gate electrode; PA1 annealing said substrate to form source and drain regions; and PA1 mounting a source electrode on said source region, and a drain electrode on said drain region.
In the above-mentioned proposed method, the gate electrode is prepared from a high melting metal in place of, for example, a conventional low melting metal such as aluminium. Therefore, the proposed method offers the advantages that no difficulties arise even when a gate electrode is already formed at the time of the heat treatment required to activate an ion-implanted layer, said gate electrode being used in this case as a mask in ion implantation, thereby ensuring the precise formation of an impurity region.
However, the proposed self-alignment method is accompanied with the drawback that the high melting metal has a high resistance; thus imposing limitations on the improvement of the high frequency property of an super high frequency transistor and, in fact, disallowing the attainment of any appreciable improvement.
Apart from the proposed self-alignment method, attempts have also been made to deposit gold on the high-melting metal in order to reduce gate resistance. However, this attempt has also been accompanied with difficulties, such that, when annealing was carried out in a furnace for the activation of an ion-implanted layer, the gold penetrated the high melting metal and reacted with the substrate, thus destroying the Shottky contact. Therefore, only a high melting metal having high electric resistance must be used as a gate electrode. As a result, it is difficult to provide an super high frequency transistor.